Testing of associated memories of the type described above, formed on semiconductor substrates, has often been done by the provision of a built-in self-test (BIST). BISTs include a state machine formed on the silicon substrate which contains the associative memories and the other VLSI circuit components such as the logic components of a microprocessor chip. Such a BIST is shown in co-pending application Ser. No. 08/398,468, filed Mar. 3, 1995, and entitled "BIST Tester for Multiple Memories" (Atty. Docket No. BU9-94-146); and a state machine for testing a DCU type memory is shown in U.S. Pat. No. 5,173,906.
In testing multiple memories, conventional prior art practice has been to surround each of the memories with latches and multiplexors and to test each memory independently, from data supplied by the state machine of the BIST or through a scan-chain from an off-chip tester. Also, conventional prior art has employed a separate BIST for each memory. While in many cases this works quite well, it does have certain drawbacks, especially in the case of testing associated memories. One such drawback is the requirement of a significant amount of chip area or "real estate" needed for forming the latches and multiplexors which bound the various memories. Another drawback is the totally independent testing of an associated memory (i.e., one that in normal operation receives a portion of its information or data, such as a portion of the address, from another memory) is that the path between the two memories is not tested. This is because the test signals to this dependent memory are separately supplied from the BIST rather than being supplied through the source memory. Thus, totally independent testing does not test the performance of the associated memories using the critical path between one memory and the other. Any problems or improper functioning of the critical data path between the two memories in the transfer of data is not detected by this type of testing since each memory is tested separately and independently from data generated from the BIST machine which does not use one memory to supply data to another memory, i.e., with the signal timings and along the path which the data flows during functional operation. While the problem of testing associated memory is extant in BIST tests, it also exists in other types of tests of memories, e.g., signals from off-chip testers applied to test memory circuits and other dependent circuits.